First-In First-Out memories (FIFOs) are used in a variety of electronic circuits for buffering data transferred between a pair of circuits that operate at different clock rates. Generally, there are two types of FIFOs. The first type of FIFO is the shift register type that uses a self-clocking register for shifting data from a write port to a read port. The second type of FIFO utilizes a Random Access Memory (RAM) as its storage element, rather than a shift register. The RAM within the RAM-type FIFO may have a single (combined) read/write port or separate (dual) ports for reading and writing data, the latter being more popular. The most common type of dual-port RAM-type FIFO utilizes a ring-type addressing mechanism comprised of a pair of n-bit shift registers (where n is an integer, corresponding to the number of storage rows in the RAM). Each shift register is associated with one of the read and write ports, respectively, of the RAM and operates to sequentially address the RAM so that a B-bit word (where B is an integer, corresponding to the number of bits in a word) may be read from, or written to, the addressed storage location, respectively. In addition, during normal operation of the FIFO, as a result of a read or write operation on a given memory location of the RAM, the FIFO causes the read or write shift register, respectively, to be incremented to address the next successive memory location in the RAM. Moreover, the input port of the RAM is coupled to a data input register that acts as a buffer to temporarily store incoming data supplied on a Data Input line before such data is supplied to the RAM input port.
From a reliability standpoint, it is desirable to test all aspects of the ring-address FIFO. In the past, FIFOs have been tested by parametric, functional and asynchronous tests. However, such tests do not reliably detect all possible faults, including faults associated with the memory, the addressing mechanism, and the overall functionality of the FIFO. Fault models and tests have been described in the literature for detecting faults in RAMs. In addition, U.S. Pat. No. 5,513,318 (hereinafter the '318 patent) to Ad. J. van de Goor and Yervant Zorian, provides a technique to detect memory, addressing and functional faults that may occur in a dual-port RAM-type ring-address FIFO. That patent is incorporated herein in its entirety by reference.
However, the method described in the '318 patent applies to a dual-port RAM-type ring-address FIFO with a standard data input register containing edge-triggered latches. In addition, the '318 patent applies to such a FIFO with Design For Testability features, including a Built-In Self-Test controller. A latch is a bistable circuit (i.e., a flip-flop) that is set and reset by appropriate input signals. It is the means by which the data input register buffers data for the input port to the RAM. An edge-triggered latch applies data present in the data input register to the input port of the RAM when a rising or falling clock edge (i.e., during a clock cycle) is detected by the latch. Accordingly, data present in the register is not automatically applied to the RAM; rather, a clock cycle during which a clock edge occurs is an additional condition.
The data input register of the dual-port RAM-type ring-address FIFO can include another type of latch, namely transparent latches. Where the register contains transparent latches, the data present in the data input register can be automatically applied to the RAM without waiting for the additional condition of a clock edge during a clock cycle applied to the data input register. Rather, transparent latches automatically apply the data to the RAM input port during an enabling level signal of the clock applied to the register (also referred to as a level sensing latches). For example, so long as the clock to the data input register has a level binary value of zero, the transparent latches cause the data present in the register to be applied to the RAM input port. Accordingly, transparent latches allow data to be written to the RAM asynchronously in that they do not require that the clock be at a certain point (either a rising or falling edge); rather, data can be moved from the register to the RAM input port independently of a clock cycle.
A data input register containing transparent latches improves the performance of the dual-port RAM-type ring-address FIFO by increasing the speed at which data is applied to the RAM. Transparent latches reduce the time necessary to apply data inputted to the data input register to the input port because a clock cycle is not necessary. Accordingly, transparent latches increase the speed at which data is available to be read (also referred to as the latency period or elimination of the pipeline stage, or the stage between clock edges necessary for use of a edge-triggered latch in the data input register).
However, a dual-port RAM-type ring-address FIFO with a data input register containing transparent latches cannot use the method of the '318 patent to detect memory, addressing and functional faults which may occur. This is because the data input register containing such transparent latches automatically applies data present in the register to the RAM when the clock to such register has an enabling level signal. Accordingly, there is a need for a technique to detect memory, addressing and functional faults that may occur in a dual-port RAM-type ring-address FIFO with a data input register containing transparent latches.